1. Field of the Invention
The present invention relates to computer sub-system interconnect systems. More particularly, the present invention relates to such interconnect systems adapted for use in computers wherein the computer design permits an application-specific choice among several different central processing units (CPUs), not all of which are installed in the computer at any one time, independent of the design of the balance of the computer system.
2. Background
A single-board computer (SBC) is one in which all the essential computer components required to perform the desired computer function are substantially contained on a single printed wiring module or board. The heart of such a machine is a central processing unit (CPU). The CPU controls the operation of the machine and performs various types of input/output (I/O) operations, calculations and logical operations in accordance with computer program instructions. In order to do so, the CPU is generally supported by memory and I/O circuits on the printed wiring module.
Single-board computers are often adapted for specific functions. For example, they may be used as controllers for other machines or large systems, and SBCs are often designed with this flexibility in mind. Included in the memory is a portion which is typically read-only, and which contains a set of customized program instructions directing the CPU to perform the specific task for which the SBC is adapted. However, the flexibility afforded by reprogramming may not be adequate to adapt current SBCs to all the tasks to which they may otherwise be successfully applied, because for sufficiently different tasks, different CPUs may be desirable. Yet, designers ordinarily cannot readily swap one CPU for another CPU better suited to a specific application or needs of a user.
Therefore, one solution to this problem has been to locate the memory and I/O circuits on a motherboard and the CPU on a very small daughterboard. In order to interconnect daughterboards carrying different CPUs to a common motherboard design, prior art technology requires that a standard CPU bus be designed and implemented. Central processing units having other than the standard CPU bus as their native interconnection scheme would be adapted by logic on the daughterboard to interface with the signals of the standard CPU bus. However, this approach has the disadvantage of requiring a sometimes significant amount of logic circuits to be present on the daughterboard to perform the adaptation and service the standard CPU bus interface.
It should be noted that the above-described problem in the prior art may also arise in computer systems other than SBCs wherein a flexible system is desired which includes the capability of swapping CPUs among CPUs of different types.